Electronic design automation (EDA) is applied in the semiconductor industry for virtually all design projects. After an idea for the product is developed, EDA tools are used to define a specific implementation including lithographic masks for production of the finished chips, in a process referred to as tape-out. The lithographic masks are then used with fabrication equipment to manufacture integrated circuit wafers. Testing and diagnosis are required steps to determine defective dies and defect localization. Next, physical failure analysis is performed to identify root causes for systematic defects which are used for correction of masks, and design and fabrication process improvements in order to increase yield. Finally, the wafers are diced, packaged and assembled to provide integrated circuit chips for distribution.
An exemplary procedure for using EDA tools begins with a design specification of a product to be implemented using the integrated circuit. Next, logic design tools are applied to create a high level description based on description languages such as Verilog or VHDL, and functional verification tools are applied in an iterative process to assure that the high-level description accomplishes the design specification. Next, synthesis and design-for-test tools are used to translate the high-level description to a netlist, optimize the netlist for target technology, and insert test logic that permits testing of the finished chips.
A typical design flow might next include a design planning stage, in which an overall floor plan for the chip is constructed and analyzed to ensure that timing parameters for the netlist can be achieved at a high level. Next, the netlist may be rigorously checked for compliance with timing constraints and with the functional definitions defined at a high level using VHDL or Verilog. After an iterative process to settle on a netlist and map the netlist to a cell library for the final design, a physical implementation tool is used for placement and routing. A tool performing placement positions circuit elements on the layout, and a tool performing routing defines interconnects for the circuit elements.
The components defined after placement and routing are usually then analyzed at the transistor level using an extraction tool, and verified to ensure that the circuit function is achieved and timing constraints are met. The placement and routing process can be revisited as needed in an iterative fashion. Next, the design is subjected to physical verification procedures, such as design rule checking (DRC), layout rule checking (LRC) and layout versus schematic (LVS) checking, that analyze manufacturability, electrical performance, lithographic parameters, and circuit correctness.
After closure on an acceptable design by iteration through design and verify procedures, like those described above, the resulting design can be subjected to resolution enhancement techniques that provide geometric manipulations of the layout to improve manufacturability. Finally, the mask data is prepared and taped out for use in producing finished products.
This design process with EDA tools includes circuitry that allows the finished product to be tested. Efficient testing of integrated circuits often uses structured design for testability (DFT) techniques. In particular, these techniques are based on the general concepts of making all or some memory elements like flip-flops and latches in the circuit under test (CUT) directly controllable and observable. The most-often used DFT methodology is based on scan chains. This approach assumes that during testing all (or almost all) memory elements are included in shift registers called scan chains. As a result, the designed logic circuit has two (or more) modes of operation, including at least a functional mode and a test mode. In the functional mode, the memory elements perform their regular functions. In the test mode, the memory elements become scan cells that are connected to form one or more scan chains. These scan chains are used to scan-in test stimuli into a CUT and scan-out test responses. Applying a test pattern consists of performing scan-in of (or loading) a test stimulus, applying one or more capture clocks, and then performing scan-out of (unloading) the captured test response. The test responses are then compared to fault-free test responses to determine whether the CUT works properly.
The DFT methodology has been widely used in order to simplify testing and diagnosis. From the point of view of automatic test pattern generation (ATPG), a CUT can be treated as a combinational or partially combinational circuit. Today, ATPG software tools are able to generate a set of test patterns based on different fault models including stuck-at, transition, path delay, bridging and cell-internal faults. When a particular fault in a CUT is targeted by an ATPG tool, only a small number of scan cells (typically less than 1 percent) is set to particular values (called hereafter care bits) and one scan cell (an observable point) is observed in order to detect this fault wherein the specified care bits are required to sensitize this fault and propagate the fault effect to the selected observable point, with the remaining scan cells being don't care bits. A common approach for test application time reduction (TATR) is for the ATPG tool to target many faults with each test pattern, therefore the percentage of care bits and the number of observe points increase. Still, on average over an entire pattern set, care bits are typically only a few percent. To further reduce TATR it is common to use compressed test data rather than storing the entire test stimulus and the entire test response in the tester.